1. Field of the Invention
The present invention relates to a semiconductor device having an electrostatic discharge (ESD) protection arrangement, which is constituted such that an internal circuit of the semiconductor device is protected from damage caused by ESD phenomena, and more particularly, to an improvement of such an ESD protection arrangement provided in a MOS type semiconductor device.
2. Description of the Related Art
In order to protect an internal circuit of a MOS type semiconductor device from damage caused by ESD phenomena, an ESD protection arrangement is provided in the MOS type semiconductor device. In the MOS type semiconductor device, each of MOS transistors may function as a parasitic bipolar transistor. Usually, each of the MOS transistors carries out a normal operation as a MOS transistor. However, when ESD phenomena occur, the MOS transistor carries out a parasitic bipolar operation, whereby an internal circuit of the MOS type semiconductor device can be protected from damage caused by the ESD phenomena.
In the MOS type semiconductor device, a multi-finger structure is used to effectively constitute the ESD protection arrangement, as disclosed in, for example, JP-A-H2-271674, WO91/05371, JP-A-2000-156501, SP6,559,507, U.S. Pat. No. 6,559,507, V. A. Vashchenko et al., “INCREASING THE ESD PROTECTION CAPABILITY OF OVER-VOLTAGE NMOS STRUCTURES BY COMB-BALLASTING REGION DESIGN” Reliability Physics Symposium Proceedings, 2003, 41st Annual. 2003 IEEE International, Mar. 30–Apr. 4, 2003, P. 261–268, and Bart Keppens, et al., “Active-Area-Segmentation (AAS) Technique for Compact, ESD Robust, Fully Silicided NMOS Design”, September, 2003.
In particular, a plurality of elongated gate electrodes are formed on the semiconductor substrate so as to be arranged in parallel to each other at regular intervals, and a high-density impurity region is formed in the semiconductor substrate at an area between two adjacent elongated gate electrodes. One of two adjacent high-density impurity regions is defined as a source region, and the other high-density impurity region is defined as a drain region, with a channel region being defined between the source and drain regions. Namely, in the multi-finger structure, one finger is defined by one of the elongated gate electrodes, and source and drain regions arranged along the respective sides of the elongated gate electrode, with a plurality of MOS transistors being produced and arranged in series along the elongated gate electrode.
When each of the drain regions is supplied with an ESD current, and when an ESD voltage exceeds a predetermined threshold voltage, an avalanche breakdown occurs at a PN junction between the drain region and the channel region, so that a substrate current flows through the semiconductor substrate. The substrate current causes a potential difference in the semiconductor substrate, so that a potential is heightened in the vicinity of the bottom of the source region with respect to a ground voltage. As a result, a PN junction at the bottom of the source region is forwardly biased so that the parasitic bipolar transistor is turned ON, resulting in considerable decline of the voltage, which is called a snapback. Thus, a source-drain resistance is decreased so that a large amount of current flows through the parasitic bipolar transistor, whereby the ESD current is safely discharged.
Nevertheless, in the prior art MOS type semiconductor device having the ESD protection arrangement, it is difficult to constitute the ESD protection arrangement so that it can operated properly, for the various reasons stated in detail hereinafter.
On the other hand, when the ESD protection arrangement is operated, an internal heating in each of the transistors mainly occurs at the PN junction area of the drain region in the vicinity of the channel region. Namely, when the ESD current flows through the PN junction between the drain region and the channel region, heat is generated at the PN junction area of the drain region in the vicinity of the channel region. Of course, the heat must be rapidly dispersed so that the ESD protection arrangement is not subjected to thermal damage. This thermal damage problem is very severe in that there is a recent trend to a lowering of process temperatures in manufacturing of semiconductor devices, resulting in inferiority of a heat-resistance of the semiconductor devices.